The fabrication of integrated circuit (IC) devices on a semiconductor wafer involves a number of steps wherein patterns are transferred from photolithographic masks to the wafer. A masking step, for example, includes an etching step that defines selected areas to be exposed on the wafer for subsequent processes such as oxidation, metal deposition and impurity introduction. With IC device and feature sizes becoming increasingly smaller, it is important for a photolithographic mask to be aligned precisely with the wafer during the masking step in order to minimize any misalignment between the layers.
Most alignment schemes utilize alignment targets or marks that are defined on the wafer during a previous processing step. Typically, each alignment target includes topographical marks, which may be formed by etching a plurality of “steps” into the wafer. These steps may have, for example, a height of about 120 nm, with a width and spacing therebetween of about 10 μm. The alignment targets are used to diffract a laser alignment beam generated by a photolithography machine (commonly known as a wafer stepper) during the masking process. The wafer stepper receives the diffraction pattern, and the relative position of the wafer and the photolithographic mask are thereafter adjusted accordingly so that the pattern of the photolithographic mask is transferred to the wafer in the precise location as desired.
Unfortunately, traditional alignment marks are increasingly becoming problematic as the IC device and feature sizes continue to become progressively smaller. For example, a misalignment of 50 nm (i.e., 0.05 μm) in a 0.6 μm gate length process only represents an 8 percent misalignment of the gate, however, this same misalignment of 50 nm (i.e., 0.05 μm) represents a 28 percent misalignment for 0.18 μm gate length process gates. This larger percentage misalignment creates many issues in today's smaller gate length devices.
Additionally, traditional alignment marks are increasingly becoming problematic as system on chip (SOC) implementations gain acceptance and usage. Some of today's SOC implementations include 0.18 μm gate length devices, in combination with shallow trench isolation (STI) structures, flash memory, etc. The traditional alignment marks not only affect the smaller gate length devices, however, they also negatively affect the flash memory devices by causing bit-line stress. It is believed that the nonuniformity of the traditional alignment marks across the wafer causes a large disparity between STI structure step heights, which may be directly linked to the aforementioned bit-line stress and flash memory failure.
Accordingly, what is needed in the art is an alignment mark, and method of manufacture therefore, that does not experience the drawbacks that traditional alignment marks experience when used with today's ever changing integrated circuit devices.